Many wireless applications, such as Bluetooth™, wireless local area networks (WLAN), cellular communications, radio frequency identifiers (RFID tags)), tire pressure monitoring systems (TPMS), etc. require low complexity phase/frequency detectors that are capable of detecting various modulated signals. Detectors based on analogue limiters and discriminators have been widely employed in some wireless applications, but they typically require large die sizes and off-chip components. Correlator-based digital phase/frequency detectors have been used in some wireless applications.
Typically, radio receivers (RX) in low power applications use frequency detection to determine whether (or not) a received signal's frequency corresponds to an expected frequency for a given radio frequency (RF) communication protocol. This determination is typically performed by continuously, i.e. at each timing period of the received signal, verifying whether (or not) each edge (e.g. a rising edge) of the received signal occurs within an expected time range when compared with a previous edge of the received signal. With such a continuous determination process, the technique requires high speed processing and a high speed reference clock, in order to yield a high performance. The use of high speed processing and a high speed reference clock, however, results in high power consumption of the frequency detector.
In this regard, the faster the determination of whether (or not) the received signal's frequency corresponds to an expected frequency for a given radio frequency (RF) communication protocol, the better is the detection. However, there is a comparable increase in power consumption, which is undesirable in handheld, mobile or power-constrained applications.
FIG. 1 illustrates a flowchart/state machine operation 100 of a known averaging frequency detection technique to verify a received signal's frequency with an average check over several received signal periods being performed. By averaging the determination over several received signal periods lower power consumption may be achieved. The state machine operation 100 starts in an idle mode at 105, with a regular determination of whether a carrier edge of a received signal is detected. If no carrier edge of a received signal is detected, the process loops at 110. If a carrier edge of a received signal is detected at 115, a timer is started and incremented at 120. The state machine operation 100 continues in an idle mode at 125, with a regular determination of whether a further carrier edge of a received signal is detected or whether an end of a time range has been reached, at 130. If an end of a time range has been reached, at 145, a reset operation is performed whereby the timer is stopped and the counter is reset, at 155. The state machine operation 100 then loops back to an idle mode at 105. If a carrier edge of a received signal is detected, at 135, a counter is incremented at 140.
For this illustration, a four-period average check is performed by verifying whether the fifth rising edge occurs within an expected time range of the fifth period. Thus, following the counter being incremented at 140, a determination of whether the counter has reached ‘five’ is performed. If the counter is less than ‘five’, at 195, the state machine operation 100 loops back to an idle mode of operation, at 125. If the counter is ‘five’, and the start of the time range has not been reached, at 150, a reset operation is performed whereby the timer is stopped and the counter is reset, at 155. The state machine operation 100 then loops back to an idle mode of operation at 105. If the counter is ‘five’, and the time range has been reached, at 160, a validation time may be performed. The validation time consists in the total duration over which the carrier has to be checked. Hence, this validation can be divided into several four-period average checks. If the confirmed total validation time range been reached, at 165, the carrier signal is identified as being valid, at 170, and a signal can be sent to other blocks to start for instance the data demodulation. The frequency detector can then be frozen until the signal sent to other blocks has been externally acknowledged as such at 185, the process being looped to 170. If the signal sent to other blocks is acknowledged as such at 190, the process loops back to an idle mode at 105. If the total validation time has not been reached, at 175, the timer is reset at 180 and the state machine loops back to an idle mode of operation at 125 to perform the next four-period average check process.
FIG. 2 illustrates an example of a timing waveform 200 of a known averaging frequency detection technique. The known averaging frequency detection technique performs an average check over a number of incoming received carrier signal edges 205 to determine whether the incoming received carrier signal is as desired, for example complies with a particular communication protocol. The known averaging frequency detection technique employs a voltage ramp 210 that starts at a first carrier signal edge of the averaging period. If the averaging is performed over four timing periods, as illustrated, the occurrence of the fifth timing carrier signal edge 225 indicates that a real clock of the incoming received carrier signal can be validated if the voltage value of the voltage ramp at the determination point resides between the first voltage reference (Ref1) 255 and the second voltage reference (Ref2) 250. This indicates the ideal timing associated with the frequency detector.
However, as illustrated, random pulses 215, 220 can also be validated even if their frequency is not correct, as the second voltage ramp 240 is determined as residing between the first voltage reference (Ref1) 255 and the second voltage reference (Ref2) 250 at the occurrence of an assumed fifth timing carrier signal edge 230 despite not being based on regular and accurate carrier edges. This error happens as the only condition for the carrier signal to be validated is that there are five instances of a clock cycle (or pulse) between the start and the end of the voltage ramp, such that the voltage level of the voltage ramp, as measured at a given point in time, resides between the first and second voltage reference 250, 255.
Thus, by employing an averaging frequency detection technique to verify the incoming received signal's frequency over several incoming received signal periods, the quality of the frequency detection operation can be greatly reduced, as employing an averaging technique allows the incoming signal frequency to vary greatly between the start and end of the averaging process (of five periods in the above illustration). Hence, although such an averaging technique requires lower speed processing and a lower speed reference clock, and thereby benefits from lower power consumption of the frequency detector, it unfortunately tends to yield a lower performance. With a noisy undesired incoming received signal, such a lower performance through an average check technique can lead to an incorrect determination that a valid incoming received signal has been received.
U.S. 20070139159 (A1) describes a clock generation circuit whereby a clock is generated synchronously to the incoming signal to check a timing of a given preamble, prior to wake up and decoding of the data received in the incoming signal. U.S. 20050237160 (A1) describes a mechanism to reduce false wake-up in a low frequency transponder, whereby a programmable smart filter detects a specific pattern at a beginning of any received incoming signal, prior to outputting the data to a controller.